| 摘要 |
The unit converts a logic address into a physical address, and has means for adding an offset address to the logic address to be converted. The adder circuit (ADD) has a logic input address (A1) and an offset input address (A2). It has at least a first (OR1) and second (OR2) registers containing offset addresses (OAD1, OAD2) and means (TR1, CMP1, MUX1) for selecting one of the offset addresses (OAD1, OAD2) on the input offset address (A1) of the adder circuit. |
