发明名称 GRAPHICS LSI
摘要 PROBLEM TO BE SOLVED: To improve the debug efficiency of a device driver which operates a fast plotting circuit and the debug efficiency of a fast plotting circuit hardware by comparing a plotting address outputted from the fast plotting circuit to a frame buffer with a stop address of a stop address register and holding the comparison result. SOLUTION: A CPU 3 issues a plot instruction to a fast plotting circuit 8. A comparator circuit 10 of a debug circuit 11 latches a memory address to a frame buffer 2 with a latch circuit 14 in a data write signal outputted by the circuit 8 to memory and compares it with the value of a stop address register 12 that stores a comparison address. A flag (address coincidence flag) 16 which shows a result of comparison performed by the circuit 10 is stored in a status register 13 and can be referred to. This makes it easier to confirm a circuit state at the time of illegal plotting, which therefore, helps make debug work efficient.
申请公布号 JPH1124960(A) 申请公布日期 1999.01.29
申请号 JP19970187766 申请日期 1997.06.27
申请人 NEC CORP 发明人 TANAKA HIDENORI
分类号 G06F11/28;G06F11/36;G06T11/00;G09G5/36;G09G5/39;G09G5/393;(IPC1-7):G06F11/28 主分类号 G06F11/28
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