| 摘要 |
PROBLEM TO BE SOLVED: To generate a clock and a frame pulse without being affected by phase shift when an active system and a stand-by system are switched by outputting a high frequency clock and a third frame pulse. SOLUTION: An output clock CLK2 of a frequency divider 32 of a PLO part 30 and a frame pulse FP2 generated in a FP generation part 50 are outputted in a clock switching circuit 2. Similarly, an output clock CLK2' of a frequency divider 32' of a PLO part 30' and a frame pulse FP2' generated in an FP generation part 50' are outputted in a clock switching circuit 2'. These outputs of the clock switching circuits 2, 2' are inputted in lower order devices 3, 3' respectively and switching of input from each of the clock switching circuits 2, 2' to each of the lower order devices 3, 3' is controlled based on control from phase monitoring parts 60, 60'. The phase monitoring devices 60, 60' are linked together and controlled so that the input is not switched by the lower order devices 3, 3' until pull-in of the PLO parts 30, 30' are completed. |
