| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing overhead in a partial scan path test circuit and adopting a high-speed clock. SOLUTION: Flip flops SC-FF 1, 2,... n for scanning are cascaded to constitute a shift register, the data input end of an SC-FF 1 is supplied with a scan-in signal from a terminal 31, and the clock ends C of the SC-FFs 1, 2,... n are supplied with a shift-only clock from a terminal 32 via an OR circuit 7. The input ends of flip flops FF 11, FF 12,... 1m for non-scanning are each supplied with a predetermined signal, the clock ends C are each supplied with a system clock from a terminal 33, and the system clock is supplied for the other input end of the OR circuit 7. In other words, the OR circuit 7 supplies either the system clock or the shift-only clock for the SC-FFs 1, 2,... n. |
