发明名称 ACTIVE ELEMENT ARRAY SUBSTRATE AND MANUFACTURE THEREOF
摘要 <p>PROBLEM TO BE SOLVED: To prevent a short circuit from occurring across packaged terminals even with the use of a thin interlayer insulating film without changing a production tact time by configuring an interlayer insulating film by forming a protrusion on an end part corresponding to each portion between packaged terminals. SOLUTION: Each active element TFT is comprised of a gate insulating film 11, a channel layer, a channel protective layer and contact layer, a resist pattern mask for patterning a picture element electrode material, and projecting part 7c of an interlayer insulating film 7 provided on an interlayer insulating film end 7b. Namely, the interlayer insulating film 7 is constituted by forming a protrusion 7c on an end corresponding to each portion between packaged terminals. Therefore, even when the interlayer insulating film 7 is formed thick, it is possible to eliminate residue in a post-process of the protrusion 7c provided between the packaged terminals which are film ends and adjacent to each other. As a result, it is possible to prevent a short circuit across the packaged terminals from occurring even if a thick interlayer insulating film 7 is used without changing a production tact time.</p>
申请公布号 JPH1124101(A) 申请公布日期 1999.01.29
申请号 JP19970175062 申请日期 1997.07.01
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIROSE TAKASHI;TAMURA TATSUHIKO;TSUBOI NOBUYUKI
分类号 G02F1/1343;G02F1/1345;G02F1/136;G02F1/1368;G09F9/30;H01L21/768;H01L23/522;(IPC1-7):G02F1/136;G02F1/134 主分类号 G02F1/1343
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