发明名称 MICROPROCESSOR CACHE CONSISTENCY
摘要 <p>A method is described of managing memory in a microprocessor system comprising two or more processors (40, 42). Each processor (40, 42) has a cache memory (44, 46) and the system has a system memory (48) divided into pages subdivided into blocks. The method is concerned with managing the system memory (48) identifying areas thereof as being 'cacheable', 'non-cacheable' or 'free'. Safeguards are provided to ensure that blocks of system memory (48) cannot be cached by two different processors (40, 42) simultaneously.</p>
申请公布号 WO1999004341(A1) 申请公布日期 1999.01.28
申请号 GB1998000142 申请日期 1998.01.16
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