发明名称 Apparatus for implementing a block matching algorithm for motion estimation in video image processing
摘要 An apparatus for implementing block matching for motion estimation in video image processing. The apparatus receives the pixel data of an original image block and the pixel data of a compared image block selected from a number of compared image blocks during video image processing. The selected image blocks are compared to determine a movement vector. The apparatus has a multi-stage pipelined tree-architecture that includes four stages. The first computational stage produces corresponding pairs of difference data and sign data. A second compression stage in the process pipeline includes a compression array that receives all the difference data and sign data, which are added together to produce compressed summation data and compressed sign data. The third summation stage in the pipeline receives the compressed summation and sign data and produces a mean absolute error for the original and compared image block pixels. A last minimization stage receives the mean absolute error for each of the compared image blocks and determines a minimum mean absolute error from among them. The compression array includes of a number of full and half adders arranged in a multi-level configuration in which none of the adder operand inputs and the carry-in inputs is left un-connected.
申请公布号 US5864372(A) 申请公布日期 1999.01.26
申请号 US19960763089 申请日期 1996.12.10
申请人 UNITED MICROELECTRONICS CORPORATION 发明人 CHEN, HONG-YI;SHU, QING-MING
分类号 H04N7/26;(IPC1-7):H04N7/32 主分类号 H04N7/26
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