发明名称 |
Memory device having divided global bit lines |
摘要 |
A memory device having a hierarchical bit line for decreasing the size of a chip, wherein a global bit line is divided into two parts. Switches are provided for selecting the divided global bit lines and sub-bit lines connected to memory cells that store data in a folded bit line structure.
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申请公布号 |
US5864497(A) |
申请公布日期 |
1999.01.26 |
申请号 |
US19970961544 |
申请日期 |
1997.10.30 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES, CO., LTD. |
发明人 |
SUH, JUNG WON |
分类号 |
G11C11/41;G11C7/18;G11C11/401;G11C11/407;(IPC1-7):G11C5/06 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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