发明名称 Tristate buffer circuit with transparent latching capability
摘要 A first output buffer circuit with independent transparent latch and tristate output capabilities includes input translators that directly drive a pair of main pull-up and pull-down output transistors. The input translators are tristatable in response to latch control signals and latching elements on side branches of the signal paths leading from the translator outputs to the output transistor gates hold the last voltage value on those signal paths at the time the translators are disabled. The main current paths through the output transistors include isolation transistors in series with the output transistors and responsive to feedback control from the buffer output. These feedback paths include logic gates responsive to output enable control signals that can shut off isolation transistors and hence put the buffer output in a high impedance state. Since neither the latch or output enable control, nor the latch elements themselves, are signal delaying components in the main signal path from the buffer input to the buffer output, throughput speed is not adversely affected.
申请公布号 US5864244(A) 申请公布日期 1999.01.26
申请号 US19970853690 申请日期 1997.05.09
申请人 KAPLINSKY, CECIL H. 发明人 KAPLINSKY, CECIL H.
分类号 H03K19/0944;(IPC1-7):H03K19/094 主分类号 H03K19/0944
代理机构 代理人
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