| 发明名称 |
Selectively enabled watchdog timer circuit |
| 摘要 |
A watchdog timer circuit includes a cyclic counter having an overflow signal that functions as a reset pulse to a microprocessor. The timer circuit includes a feature for selectively supplanting the overflow signal to enable in situ programming of the microprocessor.
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| 申请公布号 |
US5864663(A) |
申请公布日期 |
1999.01.26 |
| 申请号 |
US19960712915 |
申请日期 |
1996.09.12 |
| 申请人 |
UNITED TECHNOLOGIES CORPORATION |
发明人 |
STOLAN, JOHN |
| 分类号 |
G06F11/30;G06F1/24;G06F11/00;(IPC1-7):G06F11/00 |
主分类号 |
G06F11/30 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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