Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein

摘要

A semiconductor integrated circuit device on a semiconductor chip comprises an address bus (ABUS), a data bus (DBUS, HDBUS, LDBUS), a central processing unit (CPU) being capable of processing data of a plurality of bits, and a flash memory (FMRY) having a plurality of memory cells (MC) arranged so as to be simultaneously erasable, said flash memory including a plurality of memory arrays (ARY0-ARY7) and being responsive to accessing from said central processing unit via said address bus and providing one data of a plurality of bits within a plurality of data stored therein to said central processing unit via said data bus in a manner in which each memory array outputs one bit (D0-C7) of said plurality of bits constituting said one data.