| 摘要 |
A bi-directional data pipeline for interfacing a memory with a communications port includes a series of four pipeline elements comprising two DMA buffers and first and second holding registers. A data word is transferred from memory to the DMA buffers, each holding one data byte of the data word. With each clock cycle, the data bytes are successively transferred through the two holding registers. Two comparators are used to determine if three successive identical data bytes are present in the pipeline. If three identical bytes are detected, run length encoding is enabled, and a run length count register is incremented for each successive identical byte received through the pipeline. The run length count and associated data byte are transferred to a FIFO for transmission over the data path. A tag associated with the run length count distinguishes the run length count from data bytes in the FIFO. Data received through the FIFO is decompressed by detecting the run length count tag and loading the run length count into the run length count register. The associated data byte is loaded into one of the holding registers and copied with each successive clock cycle, decrementing the run length count register. System development tools are provided with the pipeline for debugging purposes.
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