| 摘要 |
In a memory device equipped with a redundancy circuit comprising at least one redundancy memory register storing a defective address of a defective memory element and an identifying code suitable for identifying a portion of a matrix of memory elements wherein the defective memory element is located, a circuit for transferring redundancy data of a redundancy circuit inside the memory device is provided. The circuit comprises a shared bus of signal lines provided in the memory device to interconnect a plurality of circuit blocks of the memory device and for transferring signals between the circuit blocks. The shared bus can be selectively to the various circuit blocks, and a bus assignment circuit associated to the redundancy circuit is provided for assigning, during a prescribed time interval of a read cycle of the memory device, the shared bus to the redundancy circuit whereby in the prescribed time interval the identifying code stored in the redundancy memory register can be transferred onto the shared bus.
|
