发明名称 METHOD OF AUTOMATICALLY GENERATING MASK PATTERN AND MASK
摘要 <p>PROBLEM TO BE SOLVED: To prevent shifter arrangement from discrepancy to shorten a gate length by deducting a shorten gate pattern from an active region and in addition, alternately arranging a 90-degree phase shifter and 270-degree phase shifter across a gate. SOLUTION: Firstly, a gate- and a wiring patterns are taken out of a gate part on an active region of a gate layer and a wiring part on a field oxide film. Next, a wiring pattern is obtained which is a deduction of a common part to an active region pattern from the wiring pattern. In order to accelerate a transistor, a pattern is formed in which only the gate length of the gate pattern is shorten. To resolve the shorten gate pattern, the shorten gate pattern is deducted from the active region, and a 90-degree shifter part and a 270-degree shifter part are alternately arranged across the gate in the remaining pattern. Finally, the wiring pattern, the shorten gate pattern, and the shifter pattern are summed up.</p>
申请公布号 JPH1115129(A) 申请公布日期 1999.01.22
申请号 JP19970166391 申请日期 1997.06.23
申请人 NEC CORP 发明人 TANABE YASUYOSHI
分类号 G03F1/28;G03F1/68;H01L21/027;(IPC1-7):G03F1/08 主分类号 G03F1/28
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