MODELING CIRCUIT FOR CLOCK SIGNAL HAVING NEGATIVE DELAY

摘要

PROBLEM TO BE SOLVED: To provide a modeling circuit for the clock signal having a negative delay to prevent a multi-locking phenomenon, to reduce the current consumption and also to output an accurately locked internal clock signal. SOLUTION: This modeling circuit is provided with a delay part 20 which inputs an input clock signal CLKin and produces plural delay signals CLK-D1 to CLK-Dn, a sampling/arithmetic part 30 which samples the signals CLK-D1 to CLK-Dn at the transition edge of the signal CLKin and detects that the transition edge of the signal CLKin is positioned between the transition edges of two continuous delay signals to produce the locking enable signals LE1 to LEm, and the output parts 40 and 50 which select one of signals CLK-D1 to CLK-Dn and outputs it as a modeling signal respectively by the input of signals LE1 to LEm.