| 摘要 |
<p>PROBLEM TO BE SOLVED: To keep an erasing speed constant and, further, eliminate an operation delay caused by a complex control sequence and enable the high speed erasing by a method wherein a constant erasing current is supplied from an erasing power supply circuit at the time of flash erasing. SOLUTION: In an erasing power supply circuit, in an erasing mode, a N-MOS transistor T5 is turned off and a P-MOS transistor T1 is turned on to receive an erasing power supply Vpp and an erasing voltage Vs is applied to the source side of a memory cell to practice the erasing by a tunneling effect between the source and gate. In this process, the gate of an N-MOS transistor T2 is controlled by an N-MOS transistor T3 to whose drain the erasing power supply Vpp is applied and an N-MOS depression transistor T4 so as to supply a constant current to the source side of the memory cell. Even if the erasing progresses and the threshold of the memory cell is lowered, an erasing load is not reduced.</p> |
