| 摘要 |
PROBLEM TO BE SOLVED: To suppress the inter-phase jitters of a multiphase clock by performing simultaneously the normal phase comparison between a basic clock and a phase comparison clock and the phase comparison between the basic clock and the phase comparison clock having the added prescribed delay value and performing no addition nor deletion of delay as long as the phase variance is kept within the prescribed delay value. SOLUTION: A phase comparison part 1-1 compares a basic clock with a phase comparison clock, and a phase comparison part 1-2 compares the basic clock with the phase comparison clock that is delayed via a delay element 2. Each of both parts 1-1 and 1-2 outputs a signal of a 1st level and a signal of a 2nd level when the input phases of parts 1-1 and 1-2 are coincident and not coincident with each other respectively. If a coincidence detection part 3 detects the coincidence of output signal levels between both parts 1-1 and 1-2, a delay control part 4 controls the addition or deletion of delay of a variable delay part 5. Meanwhile, the part 4 stops its control for adding or deleting the delay and keeps the preceding delay value if no coincidence is detected between both output signal levels. |
