SERIAL/PARALLEL CONVERSION CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a serial/parallel conversion circuit which suppresses the output of abnormal parallel data to be minimum even if noise is instantaneously mixed in a transfer clock signal or a data valid signal when the block of serial data of plural valid bits is intermittently inputted. SOLUTION: The serial/parallel conversion circuit 1400 outputting parallel data 1406 when a transfer bit counter 1405 which fetches serial data 1401 by referring to the data valid signal 1403 and counts the number of bits where serial data 1401 are accumulated counts a prescribed number is provided with a resetting part 1407 setting the transfer bit counter 1405 to "0" when the data valid signal 1403 shows invalidity.