| 摘要 |
PROBLEM TO BE SOLVED: To easily attain test easiness verification at a register transfer(RT) level eliminating the necessity of correction for test easiness in each execution of logical synthesis. SOLUTION: Register transfer level(RTL) circuit description data 11 for an integrated circuit to be verified are developed to a syntax analysis tree and a check point list 23 collecting signals to be check points for verifying test easiness is prepared from the syntax analysis tree together with the preparation of an external terminal list 25. Then a test pattern file 27 including description or the like for accessing a checking task 30 in addition to test pattern description is prepared based on these lists 23, 25 and timing restriction information 14. The logical simulation of the integrated circuit specified by the data 11 is executed based on the file 27. At the time, the task 30 judges whether a prescribed test easiness rule is satisfied or not based on the simulation results of the check point signals. |
