| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of multipliers by setting a coefficient to be set to each multiplier connecting to an input side 1-bit signal line to zero. SOLUTION: A 1-bit signal from an input terminal 1 is fed to multi-bit adders 30-35 through multipliers 20-25 with multi-bit coefficients (e5 -e0 ), and outputs from the adders 30-34 are sequentially fed to the adders 31-35 of a succeeding stage. An output of the adder 35 at the final stage is extracted at an output terminal 5 in 1-bit signal through a quantizer 4. Furthermore, the output of the quantizer 4 is given to a 1-bit unit delay means 6, and an output of the unit delay means 6 is fed to the adders 30-34 through multipliers 70-74 with multi-bit coefficients (d5 -d0 ). Furthermore, outputs of the adders 30-34 are fed to the adders 30-34 through multi-bit unit delay means 80-84 and outputs of the optional adders 32, 34 are fed to pre-stage adders 31, 33 through multipliers 92, 94 with multi-bit coefficients (f2 , f4 ). |
