| 摘要 |
<p>PROBLEM TO BE SOLVED: To normally execute EEPROM writing till an end and also to evade the runaway of a whole system even at the time of fetching a reset signal due to a power abnormality, etc., during EEPROM writing. SOLUTION: In a system provided with a CPU 10, an EEPROM whole circuit 11, an oscillation circuit and a reset control circuit 14, the writing operation of an EEPROM cell 1 is detected when system resetting occurs, the resetting of the EEPROM cell 1 is held till the writing operation of the EEPROM cell 1 is ended and the CPU 10 is reset at least.</p> |
