| 摘要 |
<p>PROBLEM TO BE SOLVED: To satisfy wafer process deviation only in one side to realize a high speed design by selecting a plurality of delay buses in accordance with an output of a transistor capacity determining transistor provided on a wafer to relatively adjust a timing between a clock signal and a data signal. SOLUTION: A capacity determining N-MOS transistor 301 supplies a comparator 500 via a resistive element 312 with a voltage corresponding to a transistor capacity on a wafer based on a current capacity in accordance with finishing conditions of a wafer process. The comparator 500 performs comparison with respect to a supply voltage from a constant current generating circuit 400 which is independent of the finishing conditions of the wafer process. For example, when deviations of the wafer process exist in a high speed side, an 'H' level is transmitted to a selector 700. In this case, the selector 700 selects a selection line having a large delay time among a delay element 601 composed of a plurality of selection lines having different delay time.</p> |
