| 摘要 |
PROBLEM TO BE SOLVED: To conduct the frequency drawing of PLL in relation to the phase error signal based on the most significant bit(MSB) mode. SOLUTION: A phase error signal calculating circuit (PEC) 196 generates the first error signal based on the MSB judgment mode (a method of error phase detection based on the MSB of the output of the pre-stage A/D converter of a Viterbi decoder) and its differential signal. In the period during which that differential signal and the first phase error signal accord in polarity and the absolute value of such differential signal is within a specified range, the first phase error signal is used as the second position error signal as it is, and except the above period the second position error signal is made zero. By oscillating a VCO 110 based on the second phase error signal thus generated, false lock is avoided. In the period used for the frequency drawing of PLL, a PLL mode block 197 outputs the second phase error signal selectively in a later stage. |
