| 摘要 |
The present invention relates to a level-controlled D-trigger that comprises a first (1), second (2), third (3), seventh (4), eighth (5) and ninth (6) MIS transistor as well as a fourth (8), fifth (7), sixth (9), tenth (10), eleventh (11) and twelfth (12) MIS transistor of a first and a second type, respectively. The second (2) and fourth (8) transistors are mounted in parallel between the sinks of the first (1) and fifth (7) transistors which have their power sources connected to the first (13) and second (15) supply buses, respectively. The eighth (5) and ninth (6) transistors are mounted in series between the first supply bus (13) and the inverter output (17) of the D-trigger, while the eleventh (11) and twelfth (12) transistors are mounted in series between the second supply bus (15) and the inverter output (17) of the D-trigger. This output (17) is connected to the gates of the third (3) and sixth (9) transistors which are connected in parallel to the first (1) and fifth (7) transistors, respectively. The seventh transistor (4) is connected in parallel to the eighth transistor (5) or in parallel to the eighth (5) and ninth (6) transistors which are connected in series. The tenth transistor (10) is connected in parallel to the eleventh transistor (11) or in parallel to the eleventh (11) and twelfth (12) transistors which are connected in series. The gates of the ninth (6) and tenth (10) transistors as well as the gates of the seventh (4) and twelfth (12) transistors are connected respectively to the direct clocked output (16) and to the inverter clocked output (14) of the D-trigger, wherein said outputs are connected to the sinks of the fifth (7) and first (1) transistors, respectively. The gates of the eighth (5) and eleventh (11) transistors are connected to the information input (18) of the D-trigger. The direct clock input (19) and the inverter clock input (20) of the D-trigger are connected to the gates of the second (2) and fifth (7) transistors and to the gates of the first (1) and fourth (8) transistors, respectively. This system provides for a D-trigger having a high operation reliability while reducing hardware requirements when using integrated micro-schemes based on complementary MIS techniques. |
