A process (A) for electrical contacting a silicon carbide semiconductor body surface (12), bearing a first oxide layer (3) and an overlying polysilicon layer (4) with an opening, comprises (a) thermal oxidation to form a second oxide layer (6) on the exposed surfaces of the polysilicon layer (4) and to thicken the first oxide layer (3) within the opening to less than the second oxide layer thickness; (b) etching to remove the first oxide layer (3) from the contact region (7) of the semiconductor body surface (12) and to back-etch the second oxide layer (6) by a certain amount; and (c) application of a conductive contact layer (8) on the exposed contact region (7) and on the back-etched second oxide layer (6). Also claimed is a similar process (B), in which the first oxide layer (3) is absent and in which step (a) forms a first oxide layer on the semiconductor body surface exposed within the opening and to form a thicker second oxide layer on the exposed polysilicon layer surface. Further claimed are (i) a MOS semiconductor component with a source or drain contact produced by process (A); (ii) a JFET with a contact produced by process (B) for contacting its channel region or an adjoining SiC region of the same conductivity type; and (iii) a bipolar semiconductor component with an emitter or collector region contact produced by process (B).
