3-TRANSISTOR DRAM MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To prevent a through current and reduce power consumption by setting the number of data read nodes and data write nodes of a memory cell connected to one data line of the data line pair equal to the number of data read nodes and data write nodes of the memory cell connected to the other data line. SOLUTION: A pair of data lines B00, B01 of the same column are connected to one differential amplifier and two MOS transistors for write switch and two MOS transistors for read switch are respectively connected to the data lines B00, B01. A memory cell is arranged so that the MOS transistor for write switch and MOS transistor for read switch are alternately connected to one data line to reduce the area of memory array. Moreover, a through current preventing circuit 31 prevents generation of a through current flowing between the power source voltage and grounding voltage during the write and read operation to the memory cell.