发明名称 |
HOST MICROPROCESSOR WITH APPARATUS FOR TEMPORARILY HOLDING TARGET PROCESSOR STATE |
摘要 |
Apparatus for use in a processing system having a host processor (CPU) capable of executing a first instruction set to assist in running instructions of a different instruction set which is translated to the first instruction set by the host processor (CPU) including circuitry (Gated Store Buffer) for temporarily storing memory stores generated until a determination that a sequence of translated instructions will execute without exception or error on the host processor (CPU), circuitry for permanently storing memory stores temporarily stored when a determination is made that a sequence of translated instructions will execute without exception or error on the host processor (CPU), and circuitry for eliminating memory stores temporarily stored when a determination is made that a sequence of translated instructions will generate an exception or error on the host processor (CPU).
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申请公布号 |
WO9903037(A1) |
申请公布日期 |
1999.01.21 |
申请号 |
WO1997US12058 |
申请日期 |
1997.07.11 |
申请人 |
TRANSMETA CORPORATION |
发明人 |
KELLY, EDMUND, J.;WING, MALCOLM, J. |
分类号 |
G06F9/38;C09K8/34;G06F9/30;G06F9/318;G06F9/455;G06F11/00;G06F11/14;G06F12/02;G06F12/10;(IPC1-7):G06F11/00 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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