发明名称 |
Peripheral unit selection system having a cascade connection signal line |
摘要 |
A unit address is automatically set in a peripheral unit. A plurality of peripheral units 1 are connected to a CPU unit via a signal line 3. The CPU unit accesses each peripheral unit 1 by individually selecting the peripheral units. The signal line 3 is provided with a first signal line 31 for transmitting an address by bus connection of the peripheral units and a second signal 32 line for transmitting a write command signal by cascade connection of the peripheral units 1. The write command signal is sequentially transmitted in the order in which the peripheral units 1 are connected, and only the peripheral unit 1 that has received the write command signal receives a unit address and retains it in a latch circuit 11a.
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申请公布号 |
US5862405(A) |
申请公布日期 |
1999.01.19 |
申请号 |
US19960751329 |
申请日期 |
1996.11.18 |
申请人 |
MATSUSHITA ELECTRIC WORKS, LTD. |
发明人 |
FUKUDA, ATSUO;MASUO, YASUO |
分类号 |
G06F13/14;(IPC1-7):G06F13/10;G06F13/00 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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