| 摘要 |
A byte aligner and frame synchronizer for 622 Mbit/s high speed data includes a clock divider, a data width extension circuit, a byte alignment controller, a byte alignment circuit, a pattern selector, a continuous pattern detector, a frame pulse generator, a frame sync detector, a frame sync loss detector, and frame sync error detector, and performs byte alignment very fast while also stabilizing frame synchronization by reinforcing an error correction function.
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