发明名称 Multiplexed text data sampling circuit
摘要 A multiplexed text data sampling circuit comprises a detecting signal inhibiting circuit (3) for inhibiting delivery of a detecting signal indicating a detection of a start bit of text broadcasting data from a start bit detecting circuit (2) during a predetermined period of time before the start bit appears, and a variable divider (71), responsive to the detecting signal, for dividing a clock signal so as to produce a sampling clock signal to sample the text broadcasting data, and for varying a dividing ratio between the frequency of the clock signal and the frequency of the sampling clock signal in such a manner that the sampling timing for each of bits of the text broadcasting except one or more last bits is adjusted so that each bit except the one or more last bits is sampled in the middle of a period of time during which each bit except the one or more last bits is applied to the sampling circuit, and the sampling timing for each of the one or more last bits is adjusted so that each bit of the one or more last bits is sampled at an earlier time of a period of time during which each bit of the one or more last bits is applied to the sampling circuit.
申请公布号 US5861925(A) 申请公布日期 1999.01.19
申请号 US19960747012 申请日期 1996.11.07
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 FUJITAKA, SHIGEAKI
分类号 H04N7/025;H04N7/03;H04N7/035;(IPC1-7):H04N7/08 主分类号 H04N7/025
代理机构 代理人
主权项
地址