| 摘要 |
The present invention relates to a parallel analog to digital converter (ADC) that includes at least two A/D channels which have an input and an output, where the analog input signal is converter to a digital output signal, and where each of the inputs of the A/D channels is coupled to a sample and hold unit, a multiplexing unit which includes at least two inputs, where each of the inputs is coupled to the output of the A/D channel, a time control unit for clocking the A/D channels and for controlling the multiplexing unit, wherein the analog to digital converter is provided with means for switching between a so-called idle mode and a so-called normal mode. The invention also relates to a method of saving energy in parallel analog to digital conversion. |
