发明名称 Parallelized cyclical redundancy check method
摘要 A method for encoding information bits to derive a cyclically encoded group of code bits from the information bits that were encoded, using a computer processor. A sequence of data states are generated that are the result of a series of exclusive OR operations of each of the code bits with each of the bits of a first generator word and bitwise ANDing each of the resultant bits with the results of the next previous such exclusive OR operations shifted in the direction of the least significant bit ("LSB") so as to generate a data state. The invention involves the following steps. First, an initial data state of zero is provided. Next, the LSB of the code bits is bitwise exclusive ORed with the current data state. Next, the result of the previous step is bitwise ANDed with the value n, where n is a selected binary value 2x-1, where x is any positive integer. Next, the current data state is changed to the next sequential data state by changing the data state to one of 2x predetermined data states, depending on the x LSBs of the result of the previous step. Then, both the code bits and the now current data state are shifted by x bits in the direction of the LSB; and, finally, the second through fifth of the foregoing steps are repeated until all code bits have been operated on.
申请公布号 US5862159(A) 申请公布日期 1999.01.19
申请号 US19960712007 申请日期 1996.09.11
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 SESHAN, NATARAJAN
分类号 G06F11/10;H03M13/09;(IPC1-7):G06F11/10 主分类号 G06F11/10
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