| 摘要 |
In the low power consumption data transfer bus of the present invention, the mode of division of a bus is associated with a specific layout on an actual LSI chip or an actual LSI-mounted board, and access frequency between functional blocks connected to the bus and therefore the effect of the bus division can be obtained to the maximum degree for the object of achievement of the low power consumption. Further, the operation speed of the bus (that is, data transfer speed) can be improved as compared to the case where the bus is not divided. The data transfer bus includes a bus switch circuit connected so that one data transfer bus provided between a plurality of functional blocks within an LSI is divided into three or more divisional buses, and a decoder circuit for decoding an order signal which requires two of the plurality of divisional buses during an operation of the data transfer bus, and controlling the bus switch circuit so that only the two divisional buses are connected to each other in reply to a decode output.
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