Semiconductor memory device or arrangement

摘要

In the device, every redundancy decoder (XRED) contains an arrangement for programming which redundancy decoder errors of which bank should be replaced, and an arrangement for programming as many addresses of the redundancy decoder (XRED) as should be replaced. The device has several normal registers, and an arrangement (XDEC) for activating the registers in response to an externally entered address (XADD). There are several redundant registers. A storage and comparison arrangement (XRED) contains a first arrangement for the storage of the address of one of the faulty registers available in several normal registers, as well as an arrangement for the comparison of the externally entered address (XADD) with the address of the faulty register. An arrangement (RXDC) activates a redundant register in response to an output signal from the comparator (XRED). The comparator (XRED) performs a comparison between the address of the faulty register, which is stored in the first memory arrangement, with at least a portion of the bits, which show the externally provided address (XADD). The redundant register activating arrangement may contain an arrangement for suppressing the activation of the normal register.