发明名称 |
Leiterrahmen mit reduzierter Kapazitanz für Leiter-auf-Chip-Packung |
摘要 |
<p>In a lead on chip, LOC, integrated circuit packaging arrangement (10), the conductors (46) terminate in fingers (50) that receive the bond wires (20). Adjacent the fingers (50), the conductors (46) have arm parts (52) extending over the major face of the integrated circuit (12). These arm parts (52) are formed by stamping, rolling or otherwise to present an upwardly opening channel with at least the bottom lateral margins (54, 56) of the arm part (52) raised above the plane of the bottom surface (58) of the arm part (52). This reduces sagging of the arm part (52) and capacitive interaction with the integrated circuit. <IMAGE></p> |
申请公布号 |
DE69322334(D1) |
申请公布日期 |
1999.01.14 |
申请号 |
DE1993622334 |
申请日期 |
1993.09.07 |
申请人 |
TEXAS INSTRUMENTS INC., DALLAS, TEX., US |
发明人 |
RUSSELL, ERNEST J., RICHMOND, TEXAS 77469, US |
分类号 |
H01L21/60;H01L23/495;H01L23/50;(IPC1-7):H01L23/495 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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