发明名称 |
Frame aligner including two buffers |
摘要 |
In a frame aligner, a serial/parallel converter converts an input serial data signal into a first parallel data signal. A first buffer receives the first parallel data signal to generate a first parallel data signal, and a second buffer receives the first parallel data signal to generate a second parallel data signal. A selector selects one of the first and second parallel data signals to generate a third parallel data signal. A parallel/serial converter converts the third parallel data signal into an output serial data signal. A buffer control circuit operates the first and second buffers at different phase timings in accordance with an input frame phase signal. A selector control circuit operates the selector in accordance with a difference in phase between the input frame phase signal and an output frame phase signal. |
申请公布号 |
AU7405498(A) |
申请公布日期 |
1999.01.14 |
申请号 |
AU19980074054 |
申请日期 |
1998.07.02 |
申请人 |
NEC CORPORATION |
发明人 |
HIDEAKI TAKAHASHI;KAZUO NISHITANI |
分类号 |
H04J3/06;H04L7/00;H04L7/08;H04Q11/04 |
主分类号 |
H04J3/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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