发明名称
摘要 <p>PURPOSE:To provide the logical expression evaluation computing element which executes the evaluation of a logical expression at a high speed. CONSTITUTION:The logical expression of an evaluated system is loaded in a vector register 3 as vector data expressing the respective constitutive elements with numerical values corresponding to the class and successively arranging them. The control means 41 of a logical expression evaluation computing element 4 continuously and successively reads the constitutive element of the logical expression in the form of the vector data stored in the vector register and based on the result of judging the class of each read constitutive element and the current states of respective means 43-46, when it is necessary to actually execute calculation, the calculation is executed by using an evaluated value calculating means 42. Then, the result is held in an evaluated value holding means 43 and concerning a logical expression part corresponding to the second data to be calculated of an operator for which the actual calculation become unnecessary, for example, corresponding to the second data to be calculated of an OR operator when the current intermediate evaluated value is '1', a control signal required for advancing the evaluation of the logical expression is generated while skipping the reading of that part. Then, the evaluation of the logical expression is advanced while controlling the relevant means 43-46.</p>
申请公布号 JP2845650(B2) 申请公布日期 1999.01.13
申请号 JP19910321165 申请日期 1991.11.08
申请人 NIPPON DENKI KK;NIPPON GENSHIRYOKU KENKYUSHO 发明人 NISHIKAWA TAKESHI;ASAI KYOSHI
分类号 G06F17/10;G06F17/16;G06F19/00;(IPC1-7):G06F17/10 主分类号 G06F17/10
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