发明名称 MULTI-PROCESSOR CONNECTION SYSTEM
摘要 PROBLEM TO BE SOLVED: To obtain multi-processor connection system in which a mounting area is reduced. SOLUTION: This system is provided with substrates 11, 21, and 31 and a mother board 41 on which processors 2 are respectively loaded, upward connectors 3 erected to the upward direction of the substrates, and downward collectors 4 elected to the downward direction of the substrates, and upward connectors 3 erected to the upward direction of the surface of the mother board 41. The upward connectors 3 and the downward connectors 4 are mutually connected so that the buses of the substrates 11, 21, and 31 and the mother board 41 can be hierarchically connected. Thus, the driving of each processor 2 can be attained. The processor loading substrates are vertically piled up so that a wiring pattern for connecting the processors can be made the shortest, and as a result, the influence of a reflected wave and a ringing waveform can be suppressed, and the operating frequencies of the processor bus can be improved. Also, the minimization of a mounting area can be realized.
申请公布号 JPH117348(A) 申请公布日期 1999.01.12
申请号 JP19970161737 申请日期 1997.06.19
申请人 NEC CORP 发明人 KIMURA TAKAYUKI
分类号 G06F3/00;G06F15/173;H05K1/14;H05K1/18 主分类号 G06F3/00
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