| 摘要 |
PROBLEM TO BE SOLVED: To obtain a high withstand voltage with a shallow diffused layer by coupling a first depletion layer which expands from an impurity diffused layer with a second depletion layer expanding the junction of a first conductivity-type region with a second conductivity-type well layer at the time of a reverse bias, thereby forming a unified depletion layer. SOLUTION: Source and gate terminals 28, 14A are short-circuited and reverse bias is applied between it and a drain terminal 27 so as to form first, and second depletion layers 29-1, 29-2 according to applied voltages at p-n junctions between a p-type drain layer 20 and n-type well layer 19 and between a p-type semiconductor Si substrate 1A and well layer 19. The applied voltages lower to couple the first layer 29-1 with the second layer 29-2 to form a single depletion layer 29. The voltage for forming this layer 29 is lowered below the breakdown voltages of these p-n junctions to relax the electric field and improve the withstand voltage. |
