发明名称 |
Digital PLL circuit |
摘要 |
A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.
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申请公布号 |
US5859551(A) |
申请公布日期 |
1999.01.12 |
申请号 |
US19970848675 |
申请日期 |
1997.04.29 |
申请人 |
FUJITSU LIMITED |
发明人 |
OHISHI, SYOUJI;TAMAMURA, MASAYA;HATTA, KOICHI |
分类号 |
H03L7/06;H03L7/08;H03L7/085;H03L7/091;H03L7/095;H03L7/10;H04L7/033;(IPC1-7):H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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