发明名称 MEMORY DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To achieve the high speed of a reading period and to achieve low dissipation power at the same time without increasing the area, by conducting a potential control circuit in response to the supply of a reference reading signal, and connecting a holding signal to the first power supply. SOLUTION: A basic reading signal is 1. Reading signals RA and RB both become 1 regardless of address selection. Transistors P11 and P12 of reading circuits 1 and 2 are OFF. A transistor N41 of a potential holding circuit 4A is conducted at high impedance. A transistor N42 connects a data line to the grounding potential in response to a basic reading signal RO. The holding voltage of the data line is discharged in a short time. An output DO of an inverter 3 becomes 1 in response to the discharge. When the basic reading signal RO becomes 0 and the reading signal RA is 0 and RB is 1 in correspondence with address selection at this time, the data-line holding potential becomes 0, and the output DO becomes 1. Furthermore, when the basic reading signal RO is 0, the reading signal RA is 1 and RB is 0 in correspondence with address selection, and the output DO of the inverter 3 becomes 0.</p>
申请公布号 JPH117774(A) 申请公布日期 1999.01.12
申请号 JP19970156520 申请日期 1997.06.13
申请人 NEC YAMAGATA LTD 发明人 ENDO SHINJI
分类号 G11C11/41;G11C7/00;G11C11/413;G11C11/417;(IPC1-7):G11C11/41 主分类号 G11C11/41
代理机构 代理人
主权项
地址