发明名称 |
Cache memory employing dynamically controlled data array start timing and a microcomputer using the same |
摘要 |
A comparator is constituted such that a hit signal phi hit is high, before hit check is established in each way of an address array, and such that the hit signal goes low, when a mishit has been established. When a clock frequency is relatively high, the address array is activated by the first clock signal, and thereafter, all ways of a data array are activated by the second clock signal before the hit check in the address array is established. When the hit check has been established, data read from a way in the data array which has hit is immediately outputted onto a data line and an operation in the way which has mishit is stopped. This novel constitution realizes a high-speed cache operation. When the clock frequency is relatively low, only a way in the data array that has hit is activated after completion of the hit check, thereby reducing power consumption at a low-speed operation.
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申请公布号 |
US5860127(A) |
申请公布日期 |
1999.01.12 |
申请号 |
US19960653278 |
申请日期 |
1996.05.24 |
申请人 |
HITACHI, LTD.;HITACHI ULSI ENGINEERING CO., LTD. |
发明人 |
SHIMAZAKI, YASUHISA;NAGATA, SEIICHI;NORISUE, KATUHIRO;ISHIBASHI, KOICHIRO;NISHIMOTO, JUNICHI;YOSHIOKA, SHINICHI;NARITA, SUSUMU |
分类号 |
G06F12/00;G06F12/06;G06F12/08;(IPC1-7):G06F12/06 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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