Instruction set for a content addressable memory array with read/write circuits and an interface register logic block

摘要

An associative processing memory system for concurrent data searching and concurrent data processing which includes content addressable memory (CAM) array having multiple CAM words; a multiplexer for executing one of the input devices and for passing an output of one of the input devices; an interface register logic block for storing instructions in a command register and control and status information in a control and status register; a match circuit for executing a match instruction for performing a masked comparison of data in every CAM word in the CAM array to a search pattern; a read circuit for executing a read instruction for reading one CAM word in the CAM array wherein the CAM word is selected using a response register A and a multiple response resolver (MRR); a write circuit for executing a write instruction for performing a masked write operation to every CAM word indicated by a bit set in a select vector; a shift circuit for executing a shift instruction for shifting the response register A up or down by one bit position; a clear circuit for executing an instruction for clearing the most significant bit set in the response register A; a move circuit for executing a move instruction for writing the data contents indicated by the select vector to a response register; a write-column circuit for executing an instruction for writing the contents of the select vector to a column in the CAM array; a circuit for executing an nop instruction for performing no operation; a read-shift for executing a readshift instruction; a read-snext circuit for executing a readsnext instruction; a write-shift circuit for executing a writeshift instruction; and a write-snext circuit for executing a writesnext instruction.