| 摘要 |
PROBLEM TO BE SOLVED: To reduce the memory capacity of an LSI testing apparatus and to reduce its test time when a ROM is tested. SOLUTION: In a ROM testing operation in the wafer state of microcomputer chips 100, 200, 300 in which ROM's 101, 201, 301 are built, transfer gates 109 to 120, 209 to 220, 309 to 320 which connect the adjacent chips 100, 200, 300 are provided. High-potential power supplies (VDD's), low-potential power supplies (GND's), reset signals, clock signals and ROM outputs are connected to each other. The ROM outputs of the respective chips are compared by comparison circuits 102, 202, 302. When they agree, the respective ROM's are judged to be nondefective. |
