| 摘要 |
A novel logic family, called Charge Recycling Differential Logic (CRDL) circuit, reduces power consumption by utilizing a charge recycling technique and has a speed comparable to those of conventional dynamic logic circuits. The CRDL circuit also has improved noise margin due to inherently static operation. An 8-bit Manchester carry chains and full adders were fabricated using a 0.8 mu m single-poly double-metal n-well CMOS technology. The measurement results indicate about 16-48% improvements in power-delay product are obtained compared with Differential Cascode Voltage Switch (DCVS) circuit.
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