| 摘要 |
<p>Simply constituted parallel arithmetic units capable of parallel operating complex numbers in a minimum number of cycles by using two buses. Data are inputted from data buses B1 (bus 1) and B2 (bus 2) to arithmetic units through lines (201 and 202). The inputted data are delayed by one cycle by delay elements (203, 205 and 211). Multiplexers (204 and 206) each selects one item from the inputted data and output it. Arithmetic units (207 and 208) operate the data inputted through input terminals (I1, I2, I3 and I4), and output the results of operation through output terminals (01 and 02). The arithmetic units (207 and 208) execute operations such as multiplication and addition.</p> |
