发明名称 A HIGHLY INTEGRATED MULTI-LAYER SWITCH ELEMENT ARCHITECTURE
摘要 <p>An architecture for a highly integrated network element building block (100) is provided. According to one aspect of the present invention, a network device building block (100) includes a network interface (205) with multiple ports for transmitting and receiving packets over a network. The network device building block (100) also includes a packet buffer storage (230) which is coupled to the network interface. The packet buffer storage (230) acts as an elasticity buffer for adapting between incoming and outgoing bandwidth requirements. A shared memory manager (220) may also be provided dynamically to allocate and deallocate buffers in the packet buffer storage (230) on behalf of the network interface (205) and other clients of the packet buffer storage (230). The network device building block (100) furhter includes a switch fabric (210) which is coupled to the network interface (205). The switch fabric (210) provides forwarding decisions for received packets. A given forwarding decision includes a list of ports upon which a particular received packet is to be forwarded. A central processing unit (CPU) interface (215) is also included in the network device building block (100). The CPU interface (215) is coupled to the switch fabric (210) and is configured to forward packets received from the CPU (161) based upon forwarding decisions provided by the switch fabric (210).</p>
申请公布号 WO1999000936(A1) 申请公布日期 1999.01.07
申请号 US1998013199 申请日期 1998.06.24
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