METHOD OF READING OUT VOLTAGE STORED IN THE MEMORY CELL OF FLOATING GATE

摘要

PROBLEM TO BE SOLVED: To provide a linearized memory cell in which a cell is used in the linear region of the negative feedback mode in the readout mode and the cell current changes linearly depending on the threshold of the cell by generating a cell readout voltage which linearly depends on the threshold voltage of the cell by making the cell current flow between two ends of an equivalent active MOS resistor. SOLUTION: A reference voltage VREF 2 is connected to the gate of the floating gate transistor which constitutes the EEPROPM that is the fundamental memory cell of a linearized memory cell. The VREF 2 is made equal to the sum of the highest cell threshold and the cell drain voltage VREF 1 to allow the operation of the EEPROM cell in a linear region. An operational amplifier makes the cell drain voltage equal to the reference voltage VREF 1 by a negative feedback action. Thereby The VREF 2 becomes higher than the sum of the cell threshold voltage and the cell drain voltage VREF 1 so that the EEPROM cell becomes operable in a linear mode.