| 摘要 |
PURPOSE:To suppress the deterioration of identification sensitivity due to dispersion between polyphase burst data signals by using a shift register which generates delay by a fast clock signal of (n) times the speed of a sampling clock signal. CONSTITUTION:The shift register 10 which generates the polyphase burst data signal by delaying a reception burst data signal by using the clock signal of (n) times the speed of the sampling clock, a selector circuit 11 which selects a burst data signal of one phase from the polyphase burst data signal generated at the shift register 10, and a 1/n-frequency divider circuit 12 which performs the 1/n-frequency division of the fast clock signal are provided. A data identification circuit 14 identifies a selected burst data signal of one phase by using the sampling clock outputted from the 1/n-frequency divider circuit 12. An up/down counter 13 controls the selector circuit 11. |
