发明名称 TEST CIRCUIT
摘要 PROBLEM TO BE SOLVED: To improve design quality by storing a plurality of past clock portions synchronizing the resulting output of subtractor with a reference clock, judging whether the stored plurality of subtracted result values are all the same or not and outputting a coincidence signal in the case of the same. SOLUTION: A counter 11 updates a count value synchronizing with a reference clock. A counter 12 updates a count value synchronizing the output of a voltage control type oscillator in a phase synchronous loop circuit 10 with a clock input in a phase frequency difference detector by way of a frequency divider. A subtractor 13 calculates the difference of the count values that counters 11 and 12 output, respectively. A subtraction result storing memory 14 stores a plurality of past clock portion of the subtraction results of the subtractor 13 synchronizing with the reference clock and outputs a lock detection signal in the case all the values of a plurality of the stored subtraction results are the same. With this method, lock judgment being dependent on external measuring apparatus such as oscilloscope and calculation of lock demand cycle are easily made possible.
申请公布号 JPH112666(A) 申请公布日期 1999.01.06
申请号 JP19970172873 申请日期 1997.06.13
申请人 NEC CORP 发明人 TAKESHITA YUICHI
分类号 G01R31/28;G01R31/00;H03L7/095 主分类号 G01R31/28
代理机构 代理人
主权项
地址